Testing Reversible Circuits

This paper is a review of the existing testing algorithms for reversible circuits. Although a great amount of effort has been made on finding means to build reversible gates and circuits, little research has been done on the modeling the faults of reversible circuits according to their process technology and consequently on the development of testing algorithms for reversible circuits. The existing techniques model the faulty wires in the circuit by stuck-at zero/one model. Here we review some interesting properties of reversible circuits with respect to stuck-at fault modeling and argue how they may ease the problem of testing compared to complexity of testing a classical irreversible circuit. For example it can be shown that any complete test set to detect single stuck-at faults is also a complete test for multiple stuck-at faults. Considering the high complexity of multiple faults testing, reversible circuits will benefit a great amount of cost reduction by testing tools only focusing on the single faults, knowing that multiple ones are also covered automatically.